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FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
March 2007
FMS6243
Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Features
Three Fourth-Order 8MHz (SD) Filters External Delay Control Transparent Input Clamping Dual-Video Load Drive (2Vpp, 75) AC- or DC-Coupled Inputs AC- or DC-Coupled Outputs DC-Coupled Outputs Eliminate AC-Coupling
Description
The FMS6243 Low-Cost Video Filter (LCVF) is intended to replace passive LC filters and drivers with a low-cost integrated device. Three fourth-order filters provide improved image quality compared to typical second- or third-order passive solutions. The FMS6243 can be directly driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias circuitry can be used if AC-coupled inputs are required (see the Applications section for details). Delay for each channel can be independently controlled with an external capacitor. The outputs can drive AC- or DC-coupled single (150) or dual (75) loads. DC coupling the outputs removes the need for output coupling capacitors. The input DC levels are offset approximately +280mV at the output (see the Applications section for details).
Capacitors
5V Only Lead-Free Package: TSSOP-14
Applications
Cable Set-Top Boxes Satellite Set-Top Boxes DVD Players HDTV Personal Video Recorders (PVR) Video On Demand (VOD)
Ordering Information
PbFree
Yes Yes
Part Number
FMS6243MTC14
Package
14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
Operating Temperature Range Packing Method
-40C to 85C -40C to 85C Tube Tape and Reel
FMS6243MTC14X 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
IN1 Del1 IN2 Del2 IN3 Del3
Transparent Clamp
2X
OUT1
Transparent Clamp
2X
OUT2
Transparent Clamp
2X
OUT3
8MHz, 4th-order
Figure 1. Functional Block Diagram
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0
www.fairchildsemi.com
FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Pin Assignments
DCap1 GND IN1 IN2 IN3 GND DCap2
1 2 3 4 5 6 7 14 13 12 11 10 9 8
VCC GND OUT1 OUT2 OUT3 DCap3 GND
Figure 2. Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Name
DCap1 GND IN1 IN2 IN3 GND DCap2 GND DCap3 OUT3 OUT2 OUT1 GND VCC
Type
INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT INPUT
Description
External Group Delay and Chroma/Luma Delay Adjustment for Channel 1 Must be tied to ground, do not float Video input channel 1 Video input channel 2 Video input channel 3 Must be tied to ground, do not float External Group Delay and Chroma/Luma Delay Adjustment for Channel 2 Must be tied to ground, do not float External Group Delay and Chroma/Luma Delay Adjustment for Channel 3 Filtered output for channel 3 Filtered output for channel 2 Filtered output for channel 1 Must be tied to ground, do not float +5V supply, do not float
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 2
www.fairchildsemi.com
FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC VI/O IOUT DC Supply Voltage Analog and Digital I/O
Parameter
Min.
-0.3 -0.3
Max.
6.0 VCC +0.3 50
Units
V V mA
Output Current Any One Channel, Do Not Exceed
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbols
TA VCC
Parameter
Operating Temperature Range VCC Range
Min.
-40 4.75
Typ.
Max.
85
Units
C V
5.00
5.25
Electrostatic Discharge Conditions
Symbols
HBM CDM Human Body Model Charged Device Model
Parameter
Value
8 2
Units
kV kV
Reliability Information
Symbol
TJ TSTG TL JA
Parameter
Junction Temperature Storage Temperature Range Reflow Temperature (Soldering) Thermal Resistance, Still Air JEDEC Standard Multi-Layer Test Boards,
Min.
Typ.
Max.
150
Units
C C C C/W
-65
150 260 100
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 3
www.fairchildsemi.com
FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
DC Specifications
TA = 25C, VCC = 5.0V, RS = 37.5; all inputs are AC coupled with 0.1F; all outputs are AC coupled with 220F into 150 loads; unless otherwise noted.
Symbol
ICC VIN PSRR
Parameter
Supply Current(1) Video Input Voltage Range No Load
Conditions
Min.
Typ. Max. Units
24 1.4 48 34 mA Vpp dB
Referenced to GND if DC-coupled
Power Supply Rejection Ratio DC (All Channels)
Note: 1. 100% tested at 25C.
AC Electrical Specifications
TA = 25C, VIN = 1VPP, VCC = 5.0V, RS = 37.5; all inputs are AC coupled with 0.1F; all outputs are AC coupled with 220F into 150 loads; unless otherwise noted.
Symbol
AV f1dB fC fSB DG DP THD XTALK SNR
Parameter
Channel Gain(1) -1dB Bandwidth(1) -3dB Bandwidth Attenuation (Stopband Reject) Differential Gain Differential Phase All Channels All Channels All Channels
Conditions
Min.
5.6 5.5
Typ. Max. Units
6.0 6.5 8.0 44 0.3 0.6 0.4 -70 75 6.6 dB MHz MHz dB % % dB dB
All Channels at f = 27MHz All Channels All Channels
Output Distortion (All Channels) VOUT = 1.8Vpp, 1MHz Crosstalk (Channel-to-Channel) f = 1MHz Signal-to-Noise Ratio All Channels, Chroma Weighting; 5MHz Low Pass
Note: 1. 100% tested at 25C.
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 4
www.fairchildsemi.com
FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Application Information
The FMS6243 Low-Cost Video Filter (LCVF) provides 6dB gain from input to output. In addition, the input is slightly offset to optimize the output driver performance. The offset is held to the minimum required value to decrease the standing DC current into the load. Typical voltage levels are shown in the diagram below:
I/O Configurations
For DC-coupled DAC drive with DC-coupled outputs, use this configuration:
Figure 5. DC-Coupled Inputs and Outputs Alternatively, if the DAC's average DC output level causes the signal to exceed the range of 0V to 1.4V, it can be AC-coupled as follows:
Figure 6. AC-Coupled Inputs, DC-Coupled Outputs Figure 3. Typical Voltage Levels The FMS6243 provides an internal diode clamp to support AC-coupled input signals. If the input signal does not go below ground, the input clamp does not operate. This allows DAC outputs to directly drive the FMS6243 without an AC coupling capacitor. When the input is AC-coupled, the diode clamp sets the sync tip (or lowest voltage) just below ground. The worst-case sync tip compression due to the clamp can not exceed 7mV. The input level set by the clamp combined with the internal DC offset keeps the output within its acceptable range. For symmetric signals like Chroma, U, V, Pb, and Pr, the average DC bias is fairly constant and the inputs can be AC-coupled with the addition of a pull-up resistor to set the DC input voltage. DAC outputs can also drive these signals without the AC-coupling capacitor. A conceptual illustration of the input clamp circuit is shown below: When driven by an unknown external source or a SCART switch with its own clamping circuitry, the inputs should be AC-coupled like this:
Figure 7. SCART with DC-Coupled Outputs The same method can be used for biased signals with the addition of a pull-up resistor to make sure the clamp never operates. The internal pull-down resistance is 800k 20% so the external resistance should be 7.5M to set the DC level to 500mV.
Figure 4. Input Clamp Circuit
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 5
Figure 8. Biased SCART with DC-Coupled Outputs
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FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
The same circuits can be used with AC-coupled outputs if desired. Here is the DC-coupled input with an AC-coupled output.
0V - 1.4V
DVD or STB SoC DAC Output
LCVF Clamp Inactive
75
where: VO = 2Vin + 0.280V ICH = (ICC / 3) + (VO/RL) VIN = RMS value of input signal ICC = 24mA Vs = 5V RL = channel load resistance Board layout can also affect thermal characteristics. Refer to the Layout Considerations section for more information. The FMS6243 is specified to operate with output currents typically less than 50mA, more than sufficient for a dual (75) video load. Internal amplifiers are current limited to a maximum of 100mA and should withstand briefduration, short-circuit conditions; however, this capability is not guaranteed.
Figure 9. DC-Coupled Inputs, AC-Coupled Outputs
External video source must be AC coupled
0V - 1.4V 0.1
LCVF Clamp Active
75
220
Group Delay Adjustment
The FMS6243 has the ability to independently adjust each channel for Sin X/X group delay and Chroma/Luma delay. This is accomplished by placing a capacitor from the device delay adjust pin to ground. The group delay can be adjusted from the nominal of +10ns to -80ns. This means that, under a nominal situation, a video system may have an overall group delay measurement of +50ns. If the system specification is +40ns, the FMS6243 could be used to decrease this group delay to fall well within specification with a guard band to allow for system variation. Adding a 50pF capacitor to the desired channel DCap pin (see Figure 15) generates a -20ns delay through the FMS6243, which, when summed with the +50ns of the system, gives a new system overall group delay of +30ns. It now meets the system specification with a +10ns guard band for system group delay variation. Figure 12 shows the effect on group delay by adding capacitance to the FMS6243 DCap pins. The correct capacitor can be chosen by determining the format of the video system (NTSC 3.58 or PAL 4.43), then choosing the desired group delay to sum with overall system delay. The desired delay and format line intersection is the delay capacitor needed for the DCap pins.
75
Figure 10. AC-coupled Inputs and Outputs
External video source must be AC coupled
7.5M 0.1
LCVF Bias Input
75
75
500mV +/-350mV
Figure 11. Biased AC-Coupled Inputs with AC-Coupled Outputs NOTE: The video tilt or line time distortion is dominated by the AC-coupling capacitor. The value may need to be increased beyond 220F to obtain satisfactory operation in some applications.
Power Dissipation
40
Group Delay (ns)
The output drive configuration must be considered when calculating overall power dissipation. Care must be taken not to exceed the maximum die junction temperature. The following example can be used to calculate power dissipation and internal temperature rise: Tj = TA + Pd * JA where: Pd = PCH1 + PCH2 + PCH3 and PCHx = Vs * ICH - (VO2/RL)
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 6
400kHz Ref 20 0 -20 -40 -60 -80 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0
3.58MHz
4.43MHz
10pF 20pF 30pF 40pF 50pF 60pF 70pF 80pF
3.5
4.0
4.5
5.0
Frequency (MHz)
Figure 12. Group Delay vs. Delay Cap. Value
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FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Signal Peaking Adjustment
The peaking of a video input signal can be adjusted by placing a peaking capacitor across the series-75ohm resistor on the output of the FMS6243. Where the input video signal to the FMS6243 has a soft roll-off, meaning the input video signal is attenuated at 4Mhz by -0.5dB, the Chroma/Luma gain is approximately -5% and fails a system specification of +- 2.5%. This attenuation can be adjusted by adding a 150pF capacitor across the series75ohm resistor on the output (see Figure 15). This brings the attenuation at 4.0Mhz to approximately 0dB, giving a Chroma/Luma gain of 0%. Figure 13 shows the peaking effect of adding a peaking capacitor across the series75ohm resistor. The graph shows a 10pF delay capacitor with a 10pF, 50pF, and 100pF peaking capacitor.
6.40 6.35 6.30 6.25 6.20 Gain (dB) 6.15 6.10 6.05 6.00 5.95 5.90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10pF10pF 10pF50pF
Group Delay and Peaking Adjustment Simultaneously
If both a group delay adjustment and a peaking adjustment need to be incorporated into the system design, the following methodology should be followed. Address the group delay adjustment first, then the peaking adjusment, because the group delay adjustment causes a video signal attenuation at 4Mhz.
6.35 400KHz 6.30 6.25 6.20 6.15 Gain (dB) 80pF 6.10 6.05 6.00 5.95 10pF 40pF 3.58MHz 4.43MHz
10pF100pF
5.90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Frequency (MHz)
Figure 14. Frequency Response vs. Delay Cap. Value
Frequency (MHz)
Figure 13. Frequency Response Delay Capacitor vs. Peaking Capacitor
VCC peaking Delay Cap 1 2 In1 In2 In3 3 4 5 6 7 Delay Cap DCAP1 GND1 IN1 IN2 IN3 GND2 DCAP2 VCC GND4 OUT1 OUT2 OUT3 DCAP3 GND3 14 13 12 11 10 Delay Cap 9 peaking 8 75 peaking 75
+
Out1
220F
+
Out2
220F
+
Out3
75
220F
Figure 15.
Schematic
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 7
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FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Layout Considerations
It is critical that the delay capacitor pins (1, 7, and 9) have the delay capacitor placed as close to the device pin as possible. The ground connection should be as short as possible, ideally a direct connect to the adjacent ground pin. These layout considerations create the best environment for the device and reduce noise. General layout and supply bypassing play a major role in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. The demo board is a fourlayer board with full power and ground planes. Following this layout configuration provides optimum performance and thermal characteristics for the device. For the best results, follow the steps and recommended routing rules listed below.
Thermal Considerations
Since the interior of most systems, such as set-top boxes, TVs, and DVD players, are at +70C; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location, such as directly above (top plane) or below (bottom plane), each other on the PCB.
PCB Thermal Layout Considerations
Understand the system power requirements and
environmental conditions.
Maximize thermal performance of the PCB. Consider using 70m of copper for high-power
Recommended Routing / Layout Rules
Do not run analog and digital signals in parallel. Use separate analog and digital power planes to
designs.
Make the PCB as thin as possible by reducing FR4
thickness.
Use vias in the power pad to tie adjacent layers

supply power. Traces should run on top of the ground plane at all times. No trace should run over ground / power splits. Avoid routing at 90-degree angles. Minimize clock and video data trace length differences. Include 10F and 0.1F ceramic power supply bypass capacitors. Place the 0.1F capacitor within 0.1 inches of the device power pin. Place the 10F capacitor within 0.75 inches of the device power pin. For multi-layer boards, use a large ground plane to help dissipate heat. For two-layer boards, use a ground plane that extends beyond the device body at least 0.5 inches on all sides. Include a metal paddle under the device on the top layer. Minimize all trace lengths to reduce series inductance.
together.
Remember that baseline temperature is a function of
board area, not copper thickness.
Modeling techniques provide first-order approximation.
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 8
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FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
Mechanical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 16. 14-Lead, Thin-Shrink Small Outline Package (TSSOP)
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 9
www.fairchildsemi.com
FMS6243 -- Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM E2CMOSTM EcoSPARK(R) EnSignaTM FACT Quiet SeriesTM FACT(R) FAST(R) FASTrTM FPSTM FRFET(R) GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANAR(R) PACMANTM POPTM Power220(R) Power247(R) PowerEdgeTM PowerSaverTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM The Power Franchise(R) TM TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM UHC(R) UniFETTM VCXTM WireTM
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I24
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
(c) 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 10
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